US 11,894,047 B2
Sense amplifier, memory and method for controlling sense amplifier
Chunyu Peng, Anhui (CN); Yangkuo Zhao, Anhui (CN); Wenjuan Lu, Anhui (CN); Xiulong Wu, Anhui (CN); Zhiting Lin, Anhui (CN); Junning Chen, Anhui (CN); Xin Li, Anhui (CN); Rumin Ji, Anhui (CN); Jun He, Hefei (CN); and Zhan Ying, Anhui (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and ANHUI UNIVERSITY, Hefei (CN)
Appl. No. 17/441,780
Filed by ANHUI UNIVERSITY, Anhui (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Dec. 25, 2020, PCT No. PCT/CN2020/139365
§ 371(c)(1), (2) Date Sep. 22, 2021,
PCT Pub. No. WO2022/021733, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 202010733140.5 (CN), filed on Jul. 27, 2020.
Prior Publication US 2023/0058436 A1, Feb. 23, 2023
Int. Cl. G11C 11/4091 (2006.01)
CPC G11C 11/4091 (2013.01) 18 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
an amplification module; and
an offset voltage storage unit, electrically connected to the amplification module;
wherein the amplification module comprises:
a first p-channel metal-oxide semiconductor (PMOS) transistor;
a second PMOS transistor, a source of the second PMOS transistor being connected to a source of the first PMOS transistor;
a first n-channel metal-oxide semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor and a first terminal of the offset voltage storage unit, and a gate of the first NMOS transistor being connected to a gate of the first PMOS transistor; and
a second NMOS transistor, a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor, a source of the second NMOS transistor being connected to a source of the first NMOS transistor, and a gate of the second NMOS transistor being connected to a second terminal of the offset voltage storage unit;
wherein, in an offset cancellation stage of the sense amplifier, the first PMOS transistor and the second PMOS transistor are configured as a current mirror, and the first NMOS transistor and the second NMOS transistor are both configured by using a diode connection mode, to store an offset voltage of the amplification module in the offset voltage storage unit.