US 11,894,041 B2
Electronic devices executing refresh operation based on adjusted internal voltage
Se Won Lee, Icheon-si Gyeonggi-do (KR); Tae Kyun Shin, Icheon-si Gyeonggi-do (KR); and Jun Sang Lee, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Feb. 21, 2022, as Appl. No. 17/676,644.
Application 17/676,644 is a continuation in part of application No. 17/210,009, filed on Mar. 23, 2021, granted, now 11,615,832.
Claims priority of application No. 10-2020-0166090 (KR), filed on Dec. 1, 2020.
Prior Publication US 2022/0172772 A1, Jun. 2, 2022
Int. Cl. G11C 11/406 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/4074 (2013.01); G11C 11/40622 (2013.01); G11C 11/40626 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An electronic device comprising:
an internal mode control circuit suitable for generating a burst control signal, a blocking control signal, and an internal voltage control signal based on a refresh cycle when an internal mode is performed in a self-refresh operation;
a refresh control circuit suitable for generating a refresh signal for performing a refresh operation every refresh cycle when the self-refresh operation is performed, generating the refresh signal every set cycle based on the burst control signal when the internal mode is performed, and blocking the generation of the refresh signal based on the blocking control signal; and
an internal voltage generation circuit suitable for adjusting a level of an internal voltage for the refresh operation based on the internal voltage control signal,
wherein, when the internal mode is performed, the internal mode control circuit activates the burst control signal within at least one refresh cycle whenever a burst refresh cycle elapses,
wherein the burst refresh cycle is set larger than the refresh cycle,
wherein, when the internal mode is performed, the internal mode control circuit counts an input of a refresh cycle signal and sets the burst refresh cycle in which the burst control signal is generated whenever the input of the refresh cycle signal is counted multiple times, and
wherein the refresh cycle signal is activated every refresh cycle.