US 11,894,038 B2
Memory device which generates improved write voltage according to size of memory cell
Daeshik Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 11, 2021, as Appl. No. 17/399,264.
Claims priority of application No. 10-2020-0101344 (KR), filed on Aug. 12, 2020.
Prior Publication US 2022/0051710 A1, Feb. 17, 2022
Int. Cl. G11C 11/06 (2006.01); G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, the value of the reference resistor determined by comparing a voltage drop across a first reference bit line in the first region with a voltage drop across a second reference bit line in the second region;
a voltage generator configured to generate a code value based on the value of the write voltage; and
a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.