US 11,893,951 B2
Display device configured to output gate signals to at least two gate lines at a time having output timings different from each other, and control method therefor
Sungjin Lim, Suwon-si (KR); Changhoon Kim, Suwon-si (KR); Hyejin Kim, Suwon-si (KR); and Jeongphil Seo, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 1, 2023, as Appl. No. 18/104,492.
Application 18/104,492 is a continuation of application No. PCT/KR2021/012611, filed on Sep. 15, 2021.
Claims priority of application No. 10-2020-0132580 (KR), filed on Oct. 14, 2020.
Prior Publication US 2023/0178049 A1, Jun. 8, 2023
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 3/3688 (2013.01); G09G 2340/0435 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of controlling a display device, the method comprising:
outputting gate signals through a plurality of gate lines including a first gate line, a second gate line and a third gate line; and
applying, through a plurality of data lines, a data voltage to a plurality of pixels connected with a plurality of switching elements to which the gate signals were output,
wherein the outputting the gate signals comprises:
in a first mode, sequentially outputting gate signals to the plurality of gate lines one gate line at a time to process image data in a first driving frequency; and
in a second mode, outputting gate signals to the plurality of gate lines at least two gate lines at a time to process image data in a second driving frequency higher than the first driving frequency,
wherein, in the second mode,
respective ones of the gate signals output to the plurality of gate lines at least two gate lines at a time have output timings different from each other, and
outputting the gate signals to the plurality of gate lines at least two gate lines at a time includes:
outputting a first gate signal to a plurality of switching elements connected to the first gate line through the first gate line at a first timing,
outputting a second gate signal to a plurality of switching elements connected to the second gate line through the second gate line at a second timing, and
outputting a third gate signal to a plurality of switching elements connected to the third gate line through the third gate line at a third timing,
wherein a plurality of pixels connected with the second gate line are charged by a third value based on a first value by which a plurality of pixels connected to the first gate line are charged and a second value by which a plurality of pixels connected to the third gate line are charged, and wherein the third value is different from the first value and the second value.