US 11,893,950 B2
Display device and electronic device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jan. 23, 2023, as Appl. No. 18/100,108.
Application 18/100,108 is a continuation of application No. 17/747,010, filed on May 18, 2022, granted, now 11,568,830.
Application 17/747,010 is a continuation of application No. 17/110,502, filed on Dec. 3, 2020, granted, now 11,373,609, issued on Jun. 28, 2022.
Application 17/110,502 is a continuation of application No. 16/817,860, filed on Mar. 13, 2020, granted, now 11,037,513, issued on Jun. 15, 2021.
Application 16/817,860 is a continuation of application No. 15/700,825, filed on Sep. 11, 2017, granted, now 10,593,274, issued on Mar. 17, 2020.
Application 15/700,825 is a continuation of application No. 14/670,531, filed on Mar. 27, 2015, granted, now 9,761,190, issued on Sep. 12, 2017.
Application 14/670,531 is a continuation of application No. 12/794,939, filed on Jun. 7, 2010, granted, now 8,994,636, issued on Mar. 31, 2015.
Claims priority of application No. 2009-150617 (JP), filed on Jun. 25, 2009.
Prior Publication US 2023/0154426 A1, May 18, 2023
Int. Cl. G09G 3/36 (2006.01); G09G 3/20 (2006.01); H03K 17/04 (2006.01)
CPC G09G 3/3648 (2013.01) [G09G 3/20 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/043 (2013.01); G09G 2352/00 (2013.01); H03K 17/04 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the third transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein a gate of the seventh transistor is electrically connected to a seventh wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,
wherein a gate of the eighth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring, and
wherein a gate of the ninth transistor is electrically connected to the seventh wiring.