US 11,893,653 B2
Unified memory systems and methods
Amit Rao, Bangalore (IN); Ashish Srivastava, Bangalore (IN); and Yogesh Kini, Bangalore (IN)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by Nvidia Corporation, Santa Clara, CA (US)
Filed on May 9, 2019, as Appl. No. 16/408,173.
Application 16/408,173 is a continuation of application No. 14/601,223, filed on Jan. 20, 2015, granted, now 10,319,060.
Application 14/601,223 is a continuation of application No. 14/481,802, filed on Sep. 9, 2014, granted, now 9,886,736, issued on Feb. 6, 2018.
Claims priority of provisional application 61/929,913, filed on Jan. 21, 2014.
Claims priority of provisional application 61/965,089, filed on Jan. 21, 2014.
Claims priority of provisional application 61/929,496, filed on Jan. 20, 2014.
Prior Publication US 2019/0266695 A1, Aug. 29, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/14 (2006.01); G06T 1/20 (2006.01); G06F 9/50 (2006.01); G06F 12/109 (2016.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/5016 (2013.01); G06F 12/109 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor, comprising:
one or more circuits to store one or more references to one or more graphics processing unit (GPU) physical addresses to be referenced by one or more central processing unit (CPU) virtual addresses.