US 11,893,425 B2
Disaggregated computing for distributed confidential computing environment
Reshma Lal, Portland, OR (US); Pradeep Pappachan, Tualatin, OR (US); Luis Kida, Beaverton, OR (US); Soham Jayesh Desai, Hillsboro, OR (US); Sujoy Sen, Beaverton, OR (US); Selvakumar Panneer, Portland, OR (US); and Robert Sharp, Austin, TX (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 19, 2021, as Appl. No. 17/531,005.
Application 17/531,005 is a continuation of application No. 17/133,066, filed on Dec. 23, 2020.
Claims priority of provisional application 63/083,565, filed on Sep. 25, 2020.
Prior Publication US 2022/0100582 A1, Mar. 31, 2022
Int. Cl. G06F 9/50 (2006.01); G06T 1/60 (2006.01); G06T 1/20 (2006.01); G06F 9/38 (2018.01)
CPC G06F 9/5083 (2013.01) [G06F 9/3814 (2013.01); G06F 9/5027 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to:
enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
load function drivers for the FPGA device in the TEE;
create corresponding device files in the TEE based on the FPGA enumeration data; and
handle remote MMIO reads and writes to the FPGA device via a network transport protocol.