CPC G06F 9/5016 (2013.01) [G06F 9/485 (2013.01); G06F 9/4812 (2013.01); G06F 9/4881 (2013.01)] | 19 Claims |
1. A method, comprising:
using a processor, initiating a first process in a first hardware accelerator configured to aid the processor by performing the first process, wherein initiating the first process comprises using one or more interface registers, and wherein the one or more interface registers comprises an accelerator identifier register that is used to uniquely identify the first hardware accelerator, a second hardware accelerator, and a third hardware accelerator;
using the processor, performing additional processing while the first hardware accelerator performs the first process after the processor initiates the first process and before the first process is completed;
using the processor, initiating a second process in the second hardware accelerator configured to aid the processor by performing the second process, wherein initiating the second process comprises using the one or more interface registers;
using the processor, initiating a third process in the third hardware accelerator configured to aid the processor in performing the third process, wherein the third hardware accelerator comprises a blocking accelerator that aids in the third process without using the one or more interface registers other than the accelerator identifier register; and
receiving, at the processor, an indication via the one or more interface registers to indicate that the first hardware accelerator has completed the first process and that the processor is to operate on results from the first process.
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