| CPC G06F 7/5443 (2013.01) [G06F 7/4876 (2013.01); G06F 7/49936 (2013.01); G06F 9/3893 (2013.01)] | 19 Claims |
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1. A process for a pipelined floating point multiplier-accumulator (MAC) computing a floating point result from N floating point pairs, each floating point pair comprising a floating point input and a floating point coefficient, the process comprising:
a maximum exponent controller determining a maximum exponent (MAX_EXP) value from among the N floating point pairs, the MAX_EXP value comprising a maximum sum value of an exponent of a floating point input and a corresponding exponent of a floating point coefficient;
a dot product controller for each of the associated N floating point pairs performing a process of:
generating a sign bit output from an exclusive OR (XOR) operation performed with an XOR gate on a sign bit of a corresponding floating point input and a sign bit of a corresponding floating point coefficient;
generating a normalized mantissa by the dot product controller performing a multiplication of a mantissa of a corresponding floating point input with a mantissa of a corresponding floating point coefficient, and asserting an exponent increment (EXP_INC) bit when the multiplication generates a result with a most significant bit of 1;
generating an exponent difference (EXP_DIFF) value by subtracting a sum of an exponent of the corresponding floating point input and an exponent of the corresponding floating point coefficient from MAX_EXP;
when the EXP_DIFF value is 0 and the EXP_INC bit is asserted, incrementing MAX_EXP and asserting a maximum increment (MAX_INC) bit to other dot product controllers generating a respective normalized mantissa;
when the EXP_DIFF value is not 0 and the EXP_INC bit is not asserted and the MAX_INC bit is asserted, incrementing the EXP_DIFF value;
when the EXP_DIFF value is not 0 and the EXP_INC bit is asserted and the MAX INC bit is not asserted, decrementing the EXP_DIFF value;
performing a padding step of pre-pended the normalized mantissa with at least one 0, performing a complement step of replacing a result of the padding step with a 2's complement of the result of the padding step if a corresponding sign bit output is 1, performing a shift step using a shift register which shifts the result of the complement step to the right by a number EXP_DIFF of bit positions and outputting a shifted result as an integer form fraction;
accumulating N integer form fractions to generate an adder output;
generating a floating point output by converting the adder output to a resulting sign bit and a resulting normalized mantissa derived from the adder output, thereafter outputting the resulting sign bit, an exponent derived from MAX_EXP, and the resulting normalized mantissa.
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