US 11,893,336 B1
Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip
Arvind Chokhani, Murphy, TX (US); Joseph Michael Swenton, Owego, NY (US); and Martin Thomas Amodeo, Santa Clara, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US)
Filed on Oct. 12, 2021, as Appl. No. 17/499,414.
Int. Cl. G06F 30/398 (2020.01); G06F 119/18 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2119/12 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable medium having machine-readable instructions, the machine-readable instructions comprising:
an integrated circuit (IC) test engine that:
generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design, wherein each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency that is greater than the test clock frequency; and
fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of the scan-in shift window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect of the second set of multicycle faults and/or defects.