US 11,893,332 B2
Global mistracking analysis in integrated circuit design
Wenwen Chai, Sunnyvale, CA (US); and Li Ding, San Jose, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 5, 2021, as Appl. No. 17/395,277.
Claims priority of provisional application 63/065,780, filed on Aug. 14, 2020.
Prior Publication US 2022/0050947 A1, Feb. 17, 2022
Int. Cl. G06F 30/3315 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3315 (2020.01) [G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
assigning, by a processor, a respective variation amount to each class of circuit elements in a plurality of classes of circuit elements in a circuit design, wherein each respective variation amount is a random sample obtained by randomly sampling a variation model which models random parameter variations of a class of circuit elements in the circuit design;
modifying a parameter value of each circuit element in a pair of launch path and capture path of a circuit design by a variation amount corresponding to a class of circuit elements to which the circuit element belongs, wherein a first circuit element in the launch path and a second circuit element in the capture path belong to a same class of circuit elements, and wherein the modifying comprises modifying a first parameter value of the first circuit element and a second parameter value of the second circuit element by a same variation amount; and
computing, by the processor, a timing slack for the pair of launch path and capture path based on the modified parameter values.