US 11,893,283 B2
Asynchronous process topology in a memory device
Glen E. Hush, Boise, ID (US); Richard C. Murphy, Boise, ID (US); and Honglin Sun, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,595.
Application 17/850,595 is a continuation of application No. 16/866,740, filed on May 5, 2020, granted, now 11,372,585.
Prior Publication US 2022/0326889 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/12 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 1/12 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array configured to store data and to function synchronously with a clock signal received from a host device;
a processing resource, implemented in hardware, coupled to the memory array and configured to:
execute a first process utilizing the data stored by the memory array responsive to a receipt of a signal by the apparatus, wherein the first process comprises a first layer of an artificial neural network;
determine asynchronously, without reference to a plurality of clock signals including the clock signal of the host device, that a result of the first process is greater than a threshold value; and
execute a second process, comprising logical operations, on the data responsive to the determination that the result of the first process is greater than the threshold value,. wherein the second process comprises a second layer of the artificial neural network;
wherein the second process is initiated without the host device providing an additional command.