CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G11C 7/1063 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01)] | 15 Claims |
1. A memory system, comprising:
a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and
a controller, wherein the controller is configured to obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.
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