US 11,893,271 B2
Computing-in-memory circuit
Feng Zhang, Beijing (CN); and Renjun Song, Beijing (CN)
Assigned to INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Appl. No. 17/904,619
Filed by INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES, Beijing (CN)
PCT Filed Jul. 23, 2020, PCT No. PCT/CN2020/103791
§ 371(c)(1), (2) Date Aug. 19, 2022,
PCT Pub. No. WO2021/248643, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. 202010512166.7 (CN), filed on Jun. 8, 2020.
Prior Publication US 2023/0104404 A1, Apr. 6, 2023
Int. Cl. G06N 3/063 (2023.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01); G06N 3/063 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A computing-in-memory circuit, comprising a Resistive Random Access Memory (RRAM) array and a peripheral circuit, wherein
the RRAM array comprises a plurality of memory cells arranged in an array pattern, and each memory cell is configured to store a data of L bits, L being an integer not less than 2;
the peripheral circuit is configured to, in a storage mode, write more than one convolution kernels into the RRAM array, and in a computation mode, input elements that need to be convolved in a pixel matrix into the RRAM array and read a current of each column of memory cells, wherein each column of memory cells stores one convolution kernel correspondingly, and one element of the convolution kernel is stored in one memory cell correspondingly, and one element of the pixel matrix is correspondingly input into a word line that a row of memory cells connect.