US 11,893,251 B2
Allocation of a buffer located in system memory into a cache memory
Rohit Natarajan, Sunnyvale, CA (US); Jurgen M. Schulz, Pleasanton, CA (US); Christopher D. Shuler, Davis, CA (US); Rohit K. Gupta, Santa Clara, CA (US); Thomas T. Zou, Millbrae, CA (US); and Srinivasa Rangan Sridharan, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 31, 2021, as Appl. No. 17/462,812.
Prior Publication US 2023/0062917 A1, Mar. 2, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/0831 (2016.01)
CPC G06F 3/0631 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0835 (2013.01); G06F 2212/1021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium having instructions stored thereon that are executable by a computer system, that includes a cache memory circuit, to perform operations comprising:
allocating a plurality of storage locations in a system memory of the computer system to a buffer; and
issuing a plurality of memory transactions in a particular order for accessing content from respective storage locations of the plurality of storage locations, wherein the particular order is different from a linear order, wherein receiving content from respective ones of the plurality of memory transactions causes the cache memory circuit to cache the content from subsets of the plurality of storage locations of the buffer in the particular order;
tracking a cache miss rate associated with memory transactions that access storage locations of the plurality of storage locations; and
in response to determining that the tracked cache miss rate satisfies a threshold rate, modifying the particular order for a subsequent use.