US 11,893,243 B2
Storage system and method for program reordering to mitigate program disturbs
Daniel J. Linnen, Naperville, IL (US); Prakash Subedi, San Jose, CA (US); Khanfer A. Kukkady, San Jose, CA (US); and Mark Murin, Kfar Saba (IL)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Oct. 6, 2021, as Appl. No. 17/495,015.
Prior Publication US 2023/0106371 A1, Apr. 6, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A storage system comprising:
a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer and wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments; and
a controller configured to:
for each of a plurality of program cycles, change, in each of the plurality of wordlines and with respect to a prior wordline, which of the plurality of programming segments is a last programming segment programmed;
after the plurality of program cycles, observe a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;
based on the observed pattern, select the certain programming segment to be the last programming segment programmed;
detect a number of program disturb errors in the memory; and
correct the program disturb errors using the error correction operation.