US 11,893,240 B2
Reducing latency in pseudo channel based memory systems
Shyamkumar Thoziyoor, San Diego, CA (US); Pankaj Deshmukh, San Diego, CA (US); Jungwon Suh, San Diego, CA (US); and Subbarao Palacharla, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 28, 2021, as Appl. No. 17/452,606.
Prior Publication US 2023/0136996 A1, May 4, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0635 (2013.01); G06F 3/0679 (2013.01)] 26 Claims
OG exemplary drawing
 
19. A pseudo channel based memory system, comprising a plurality of pseudo channels, including a first pseudo channel,
wherein the pseudo channel based memory system is configured to:
receive a memory access command targeting the first pseudo channel;
use a first pseudo channel data bus and a second pseudo channel data bus concurrently to implement the memory access command; and
receive a mode register write command configured to cause the pseudo channel based memory system to handle a successive memory access command as a low latency type memory access command, wherein the memory access command targeting the first pseudo channel is a successive memory access command to the mode register write command.