CPC G06F 3/0611 (2013.01) [G06F 3/068 (2013.01); G06F 3/0659 (2013.01); G06F 12/02 (2013.01); G06F 13/1615 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G06F 15/7821 (2013.01)] | 20 Claims |
1. A memory system, comprising:
a high-bandwidth memory (HBM) apparatus comprising processing-in-memory (PIM) functionality;
wherein the HBM apparatus comprises a logic circuit that:
receives a first command and a second command from a host device using a first interface, wherein the first command has a first type and the second command has a second type; and
converts the first command to a first PIM command according to a first PIM protocol based on the first type;
converts the second command to a second PIM command according to a second PIM protocol based on the second type; and
initiates transmission of the first PIM command and the second PIM command to the PIM functionality using a second interface;
wherein the logic circuit provides, to the host, an estimated completion time for an execution of the first PIM command; and
the logic circuit receives a third command from the host using the first interface, based on the estimated completion time.
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