US 11,893,122 B2
Shapeshift data encryption methods and systems
William David Schwaderer, Sparks, NV (US)
Appl. No. 18/000,798
Filed by William David Schwaderer, Sparks, NV (US)
PCT Filed Jun. 2, 2021, PCT No. PCT/US2021/035537
§ 371(c)(1), (2) Date Dec. 5, 2022,
PCT Pub. No. WO2021/247766, PCT Pub. Date Dec. 9, 2021.
Claims priority of provisional application 63/035,527, filed on Jun. 5, 2020.
Prior Publication US 2023/0222229 A1, Jul. 13, 2023
Int. Cl. G06F 21/72 (2013.01); G06F 21/76 (2013.01); G06F 21/60 (2013.01); G06F 21/78 (2013.01); G06F 21/71 (2013.01); H04L 9/22 (2006.01)
CPC G06F 21/602 (2013.01) [G06F 21/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a plurality of processing Cores;
a Package Interconnect communicatively coupled with the plurality of processing Cores;
a Configurable LFSR PRV Generator Hardware Array means communicatively coupled with the Package Interconnect and configured to provide a plurality of LFSRs whose length, feedback polynomial, jitter value, warm up cycle count, and algorithmic feedback discard method are configurable through a register-interface accessible by the Cores through the Package Interconnect;
a Galois Multiplication Hardware Accelerator means communicatively coupled with the Package Interconnect and configured to accelerate Galois Finite Field multiplication of two multiplicands and primitive polynomial modulus division operations necessary to identify Galois Finite Field multiplicative product values;
an Extended Euclidian Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect and configured to provide Extended Euclidian Algorithm acceleration; and
a Fischer-Yates Shuffle Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect and configured to provide fragments both fixed- size and variable-sized mince shuffling and random bit blending hardware acceleration.