US 11,893,112 B2
Quantitative digital sensor
Sylvain Guilley, Paris (FR); Adrien Facon, Paris (FR); and Nicolas Bruneau, Montrouge (FR)
Assigned to SECURE-IC SAS, Cesson-Sevigne (FR)
Appl. No. 16/954,507
Filed by SECURE-IC SAS, Cesson-Sevigne (FR)
PCT Filed Nov. 21, 2018, PCT No. PCT/EP2018/082062
§ 371(c)(1), (2) Date Jun. 16, 2020,
PCT Pub. No. WO2019/129439, PCT Pub. Date Jul. 4, 2019.
Claims priority of application No. 17306945 (EP), filed on Dec. 27, 2017.
Prior Publication US 2021/0004461 A1, Jan. 7, 2021
Int. Cl. G06F 21/55 (2013.01); G06N 20/00 (2019.01); G06F 11/30 (2006.01); G06F 21/75 (2013.01); G01R 31/317 (2006.01); G06F 11/34 (2006.01)
CPC G06F 21/554 (2013.01) [G01R 31/31719 (2013.01); G06F 11/3003 (2013.01); G06F 11/3058 (2013.01); G06F 11/3082 (2013.01); G06F 11/3495 (2013.01); G06F 21/75 (2013.01); G06N 20/00 (2019.01); G06F 2221/034 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A device for protecting an Integrated Circuit from perturbation attacks, wherein the device comprises;
a sensing unit configured to detect a perturbation attack, said sensing unit comprising a set of digital sensors comprising at least two sensors, the sensors being arranged in parallel, each digital sensor providing a digitized bit output having a binary value, in response to input data, the sensing unit being configured to deliver at least one binary vector comprising a multi-bit value, said multi-bit value comprising at least two bit outputs provided by said set of digital sensors, the device further comprising;
an analysis unit, the analysis unit being configured to receive at least one binary vector provided by said sensing unit, the analysis unit being configured to detect the perturbation attack from said at least one binary vector,
wherein each sensor of the sensing unit is implemented in a form of a digital circuit comprising an input memory block for storing the input data, a first data path for propagating the input data and forming a first delay chain, and a second data path for propagating the input data and forming a second delay chain, the input memory block and the second data path further comprising combinatorial cells configured to determine the bit output of said sensor using the input data,
wherein the device further comprises an output memory configured to store the bit outputs delivered by said sensors, the output memory comprising an output memory element associated with each sensor for storing the bit output delivered by said sensor,
wherein an i-th component of a binary vector is a bit output O_i delivered by a n i-th sensor or an output bit derived from the one or more output bits delivered by the sensors, and
wherein the device comprises an analysis unit configured to determine, in response to a detection of the perturbation attack, a quantity Q representing a quantitative estimation of the detected perturbation attack and/or a classification of the detected perturbation attack from said at least one binary vector.