US 11,893,078 B2
Analog dot product multiplier
Aravinth Kumar Ayyappannair Radhadevi, Hyderabad (IN); and Sesha Sairam Regulagadda, Hyderabad (IN)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Ceremorphic, Inc., San Jose, CA (US)
Filed on Aug. 29, 2020, as Appl. No. 17/006,815.
Prior Publication US 2022/0066740 A1, Mar. 3, 2022
Int. Cl. G06F 17/16 (2006.01); G06F 7/544 (2006.01); G06G 7/16 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 7/5443 (2013.01); G06G 7/16 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A dot product multiplier for multiplying a 1×m A matrix with an m×m B matrix to form a dot product, each element of the A matrix and each element of the B matrix comprising a sign bit and value bits, the dot product multiplier comprising:
a clock generator providing four non-overlapping phases of clock per clock cycle, the four phases being PH1, PH2, PH3, PH4;
a plurality of processing elements arranged in said m columns and said m rows, each processing element receiving an ‘a’ element of the A matrix and a ‘b’ element of the B matrix and generating a processing element output;
each processing element comprising:
a sign voltage source providing a sign voltage which is a positive voltage for positive multiplication results and a comparatively negative voltage for negative multiplication results based on a sign bit of the ‘a’ element and sign bit of the ‘b’ element;
a bit multiplier for each particular ‘a’ element value bit an and each ‘b’ element value bit bn, each bit multiplier having an output, the bit multiplier comprising:
a capacitor having a capacitance Cref*2n, the capacitor initialized to the sign voltage during the first clock phase PH1 if an=1, and initialized to 0V if an=0;
the bit multiplier coupling the capacitor to capacitors of other bit multipliers during the second clock phase PH2;
the bit multiplier zeroing the charge on the capacitor if bn=0 on the third clock phase PH3;
the bit multiplier coupling the capacitor of the bit multiplier to the processing element output during the fourth phase PH4;
each of the m columns having an accumulator, the accumulator receiving a transferred charge from the bit multiplier outputs in a respective column during the fourth phase PH4;
each accumulator converting the transferred charge to a digital value indicating a dot product value for an associated column.