US 11,892,972 B2
Synchronization mechanisms for a multi-core processor using wait commands having either a blocking or a non-blocking state
Aaron Debattista, Cambridge (GB); and Jared Corey Smolens, Santa Clara, CA (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Apical Limited, Cambridge (GB); and Arm Limited, Cambridge (GB)
Filed on Sep. 8, 2021, as Appl. No. 17/469,311.
Prior Publication US 2023/0077301 A1, Mar. 9, 2023
Int. Cl. G06F 15/82 (2006.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 15/82 (2013.01) [G06F 8/458 (2013.01); G06F 9/30087 (2013.01); G06F 9/3851 (2013.01); G06F 9/4881 (2013.01); G06F 9/526 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for synchronising processing in a multi-core processor, comprising:
receiving a command stream which comprises a plurality of commands including one or more wait commands and one or more setup commands, wherein each wait command has an associated state and one or more associated conditions;
sequentially processing each command in the command stream until a wait command is reached;
adding said wait command to a wait queue; and
checking the state associated with the wait command to be processed,
wherein if said state is a blocking state, further processing of commands in the command stream is paused until each of said wait command's associated conditions are met,
wherein if said state is a non-blocking state, a next command in the command stream is retrieved and processed, wherein when said next command is a setup command, processing of said next command comprises sending said setup command to one or more cores of the multi-core processor for implementation, and
wherein when all of said wait command's one or more associated conditions are met, said wait command is removed from the wait queue.