US 11,892,966 B2
Multi-use chip-to-chip interface
Krishnan Srinivasan, San Jose, CA (US); Ygal Arbel, Morgan Hill, CA (US); and Sagheer Ahmad, Cupertino, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Dec. 14, 2021, as Appl. No. 17/551,132.
Application 17/551,132 is a continuation in part of application No. 17/454,450, filed on Nov. 10, 2021, abandoned.
Prior Publication US 2023/0141709 A1, May 11, 2023
Int. Cl. G06F 13/36 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 2213/0016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
an anchor IC comprising a:
a processor IC; and
a memory IC configured to store one or more programs that, when executed by the processor IC, perform one or more operations;
a plurality of chiplet ICs configured to provide a function when coupled with the anchor IC via a plurality of chip-to-chip (C2C) interfaces residing in the anchor IC and the chiplet ICs, each chiplet IC comprising:
one or more requirements for a corresponding C2C interface of the plurality of C2C interfaces via which the chiplet IC connects to the anchor IC; and
one or more performance requirements for the anchor IC, and wherein each of the plurality of C2C interfaces of the anchor IC is configured to:
receive data from one chiplet IC of the plurality of chiplet ICs regardless of a functionality of the one chiplet; and
individually couple the one chiplet IC to the anchor IC; and
wherein the one or more operations comprise a programmable option for the anchor IC to interface in different combinations and arrangements of the chiplet ICs to provide different functions.