US 11,892,955 B2
System and method for bypass memory read request detection
Sanjay Goyal, Roseville, CA (US); Larrie Simon Carr, Kelowna (CA); and Patrick Bailey, Port Coquitlam (CA)
Assigned to Microchip Technology Inc., Chandler, AZ (US)
Filed by Microchip Technology Inc., Chandler, AZ (US)
Filed on May 10, 2022, as Appl. No. 17/741,282.
Claims priority of provisional application 63/195,455, filed on Jun. 1, 2021.
Prior Publication US 2022/0382688 A1, Dec. 1, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 11/10 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1621 (2013.01) [G06F 11/1004 (2013.01); G06F 13/1668 (2013.01); G06F 13/4221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for bypass memory read request detection, the method comprising:
receiving a plurality of data packets at a physical layer of a CXL memory controller;
deriving a plurality of Compute Express Link (CXL) flow control units (flits) from the plurality of data packets received at the physical layer of a CXL memory controller;
transmitting each of the received plurality of CXL flits to read bypass detection logic of the CXL memory controller;
analyzing each of the plurality of CXL flits at the read bypass detection logic to identify a bypass memory read request from the plurality of CXL flits;
transmitting the bypass memory read request over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller;
when a read request queue of the CXL memory controller is empty, generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to the bypass memory read request received at the transaction/application layer of the CXL memory controller;
receiving read data from the memory device at the transaction/application layer in response to the memory read command; and
when there is a link layer memory read request at the transaction/application layer that matches the bypass memory read request that generated the memory read command, forwarding the read data received at the transaction/application layer to the link layer of the CXL memory controller.