US 11,892,950 B2
Data prefetching for graphics data processing
Vikranth Vemulapalli, Folsom, CA (US); Lakshminarayanan Striramassarma, Folsom, CA (US); Mike MacPherson, Portland, OR (US); Aravindh Anantaraman, Folsom, CA (US); Ben Ashbaugh, Folsom, CA (US); Murali Ramadoss, Folsom, CA (US); William B. Sadler, Folsom, CA (US); Jonathan Pearce, Portland, OR (US); Scott Janus, Loomis, CA (US); Brent Insko, Portland, OR (US); Vasanth Ranganathan, El Dorado Hills, CA (US); Kamal Sinha, Folsom, CA (US); Arthur Hunter, Jr., Cameron Park, CA (US); Prasoonkumar Surti, Folsom, CA (US); Nicolas Galoppo von Borries, Portland, OR (US); Joydeep Ray, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); ElMoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Altug Koker, El Dorado Hills, CA (US); Sungye Kim, Folsom, CA (US); Subramaniam Maiyuran, Gold River, CA (US); and Valentin Andrei, San Jose, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 15, 2022, as Appl. No. 17/865,666.
Application 17/865,666 is a continuation of application No. 17/161,465, filed on Jan. 28, 2021, granted, now 11,409,658.
Application 17/161,465 is a continuation of application No. 16/355,015, filed on Mar. 15, 2019, granted, now 10,909,039, issued on Feb. 2, 2021.
Prior Publication US 2023/0051190 A1, Feb. 16, 2023
Int. Cl. G06F 12/084 (2016.01); G06F 12/0862 (2016.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 12/0862 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/608 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processors including one or more graphics processing units (GPUs);
one or more caches to provide storage for the one or more processors, the one or more caches including an instruction cache to receive instructions for execution; and
a hardware prefetcher;
wherein the apparatus to provide prefetching for the instruction cache including:
receiving a command to load block instructions in instruction code,
commencing execution of a current kernel for an application, a driver for the application being aware of a next kernel for the application to follow the current kernel, and
upon commencing execution of the current kernel, issuing a prefetch for the next kernel for execution, the prefetch for the next kernel being made directly into the instruction cache.