US 11,892,948 B2
System-on-a-chip (SoC) based fast path enabler for data applications
Ankit Jindal, Pune (IN); Pranavkumar Govind Sawargaonkar, Pune (IN); and Sriram Rajagopal, Karnataka (IN)
Assigned to EdgeQ, Inc., Santa Clara, CA (US)
Filed by EdgeQ, Inc., Santa Clara, CA (US)
Filed on Mar. 27, 2022, as Appl. No. 17/705,334.
Prior Publication US 2023/0305959 A1, Sep. 28, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 15/78 (2006.01)
CPC G06F 12/0811 (2013.01) [G06F 9/30047 (2013.01); G06F 9/5016 (2013.01); G06F 12/0862 (2013.01); G06F 15/7807 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for data packet processing comprising:
learning, at a fast path enabler, architecture information about a system-on-a-chip (SoC), the SoC comprises multiple clusters with each cluster comprising multiple cores;
communicating, from a packet dispatcher thread, to the fast path enabler resource allocation information of the SoC regarding a packet processing agent to be involved in data packet sharing; and
pre-fetching, by the fast path enabler, one or more packets from a memory into a common cache, identified among multiple common caches in the SoC based on the learned architecture information and the resource allocation information, in a preparation for running the packet processing agent.