CPC G06F 1/12 (2013.01) [G06F 13/4291 (2013.01); G06F 2213/0016 (2013.01); G06F 2213/0042 (2013.01)] | 18 Claims |
1. A clock synchronization system comprising:
a host circuit comprising:
a first clock generator configured to generate a first clock signal;
a first input output interface;
a first communication interface; and
a first processor configured to:
output a trigger signal through the first input output interface;
record a first clock count of the first clock generator simultaneously when the trigger signal is issued; and
output the first clock count from the first communication interface; and
a slave circuit comprising:
a second clock generator configured to generate a second clock signal;
a second input output interface coupled to the first input output interface configured to receive the trigger signal;
a second communication interface coupled to the first communication interface; and
a second processor configured to:
record a second clock count of the second clock generator when the trigger signal is received from the second input output interface; and
calculate a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.
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