CPC G06F 1/06 (2013.01) | 8 Claims |
1. A clock generator device, comprising:
a first clock generator circuit, having a first starting voltage, generating a first clock signal in response to a supply voltage;
a second clock generator circuit, having a second starting voltage, generating a second clock signal in response to the supply voltage, wherein the first starting voltage is lower than the second starting voltage;
a first detector circuit, detecting the second clock signal to generate a validation signal;
a selection circuit, selectively outputting one of the first clock signal and the second clock signal according to the validation signal;
a second detector circuit, detecting the first clock signal to generate a first control signal;
a first delay circuit, for delaying the validation signal to generate a first signal;
a second delay circuit, for delaying the first control signal to generate a second signal; and
a logic gate circuit, for generating a second control signal according to the first signal and the second signal;
wherein, a delay time of the first delay circuit is less than a delay time of the second delay circuit.
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