US 11,892,715 B2
Engineered electro-optic devices
Yong Liang, Niskayuna, NY (US); Mark G. Thompson, San Jose, CA (US); Chia-Ming Chang, Palo Alto, CA (US); and Vimal Kumar Kamineni, Fremont, CA (US)
Assigned to Psiquantum, Corp., Palo Alto, CA (US)
Filed by PSIQUANTUM, CORP., Palo Alto, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/552,240.
Application 17/552,240 is a continuation of application No. 17/083,141, filed on Oct. 28, 2020, granted, now 11,226,507.
Claims priority of provisional application 62/927,373, filed on Oct. 29, 2019.
Prior Publication US 2022/0107518 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G02F 1/035 (2006.01); G02F 1/225 (2006.01); G02B 6/12 (2006.01)
CPC G02F 1/035 (2013.01) [G02F 1/225 (2013.01); G02B 2006/12142 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wafer comprising:
a substrate comprising silicon or germanium;
a buffer layer coupled to the substrate and configured to relieve stress within the wafer; and
a layer stack disposed on a top surface of the buffer layer, the layer stack including:
a plurality of electro-optic material layers; and
a plurality of interlayers interleaved with the plurality of electro-optic material layers,
wherein the plurality of interlayers maintains a first lattice structure at a room temperature and at a cryogenic temperature; and
wherein the plurality of electro-optic material layers are under tensile stress and maintain a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.