US 11,892,508 B2
Joint test action group transmission system capable of transmitting data continuously
Chen-Tung Lin, HsinChu (TW); and Yuefeng Chen, Suzhou (CN)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on Nov. 10, 2020, as Appl. No. 17/094,770.
Claims priority of application No. 201911141023.3 (CN), filed on Nov. 20, 2019.
Prior Publication US 2021/0148978 A1, May 20, 2021
Int. Cl. G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/318555 (2013.01) [G01R 31/31705 (2013.01)] 14 Claims
OG exemplary drawing
 
14. A joint test action group (JTAG) transmission system comprising:
a slave unit comprising:
a test access port (TAP) circuit comprising a data input terminal, a clock terminal, a mode selection terminal, and a test data register set
a memory; and
a memory interface controller coupled to the test access port circuit and the memory, and configured to store data transmitted from the test access port circuit to the memory; and
a host unit coupled to the data input terminal, the clock terminal, and the mode selection terminal, and configured to transmit a download instruction set to the test access port circuit to have the test access port circuit select the test data register set, and have the test access port circuit enter a data shift status to receive a data package through the test data register set;
wherein:
the data package comprises an address, at least one piece of write data, and a checking code; and
during a process of receiving the data package, the test access port circuit remains in the data shift status to continuously receive the address and the at least one piece of write data in the data package.