US 11,892,504 B1
Method and system for debugging metastability in digital circuits
Alberto Arias Drake, Seville (ES); Bijitendra Mittra, West Bengal (IN); and Keyliane da Silva Fernandes Silvano, Belo Horizonte (BR)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Sep. 22, 2022, as Appl. No. 17/950,983.
Int. Cl. G01R 31/00 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/31704 (2013.01) [G01R 31/31727 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for debugging a design under test (DUT) for metastability issues using formal verification, the method comprising:
determining, by a server, that a functionality of the DUT failed an assertion;
generating, by the server, a plurality of first waveforms for a plurality of clock domain crossing (CDC) pairs that are in a cone of influence (COI) of the assertion;
applying, by the server, a constraint including a condition to the plurality of first waveforms; and
generating, by the server, one or more second waveforms for a first subset of the plurality of CDC pairs, wherein the first subset of the CDC pairs satisfied the condition.