US 11,892,502 B2
Through-silicon via (TSV) fault-tolerant circuit, method for TSV fault-tolerance and integrated circuit (IC)
Cheng-Jer Yang, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Feb. 2, 2021, as Appl. No. 17/165,797.
Application 17/165,797 is a continuation of application No. PCT/CN2019/102800, filed on Aug. 27, 2019.
Claims priority of application No. 201811012348.7 (CN), filed on Aug. 31, 2018; and application No. 201821427928.8 (CN), filed on Aug. 31, 2018.
Prior Publication US 2021/0156908 A1, May 27, 2021
Int. Cl. G01R 31/28 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC G01R 31/2884 (2013.01) [H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a plurality of operational TSVs;
a spare TSV;
a plurality of fault-tolerance control modules, each coupled to one of the plurality of operational TSVs and the spare TSV; and
a decoder, coupled to the plurality of fault-tolerance control modules,
wherein the plurality of fault-tolerance control modules are configured to deactivate one of the plurality of operational TSVs that is determined to be defective and activate the spare TSV based on a positioning code for the defective operational TSV from the decoder,
wherein each of the plurality of fault-tolerance control modules comprises:
an input control unit, coupled to an input of one of the plurality of operational TSVs and an input of the spare TSV,
wherein the input control unit is configured to deactivate the operational TSV that is determined to be defective and activate the spare TSV based on the positioning code for the defective operational TSV from the decoder.