US 11,892,501 B1
Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns
Arvind Chokhani, Murphy, TX (US); Joseph M. Swenton, Owego, NY (US); and Martin Amodeo, Santa Clara, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jul. 14, 2022, as Appl. No. 17/865,104.
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/287 (2013.01) [G01R 31/2879 (2013.01); G01R 31/2882 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable medium having machine-readable instructions, the machine-readable instructions comprising:
an integrated circuit (IC) test engine that generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design, where N is an integer greater than or equal to two; and
a diagnostics engine that:
receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by automatic test equipment (ATE), in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;
employs a fault simulator to:
fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects; and
fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with test patterns that have one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns; and
scores candidate fault and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.