US 10,560,892 B2
Advanced graphics power state management
Eric C. Samson, Folsom, CA (US); Murali Ramadoss, Folsom, CA (US); and Marc Beuchat, Yakum (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 8, 2019, as Appl. No. 16/243,029.
Application 16/243,029 is a continuation of application No. 15/720,906, filed on Sep. 29, 2017, granted, now 10,178,619.
Prior Publication US 2019/0215769 A1, Jul. 11, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 52/02 (2009.01); H04B 7/06 (2006.01); H04M 1/73 (2006.01); H04W 52/18 (2009.01); G06T 1/20 (2006.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01)
CPC H04W 52/0225 (2013.01) [G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06T 1/20 (2013.01); H04W 52/18 (2013.01); G06T 2200/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
measurement logic, at least a portion of which is in hardware, to detect information about idle transitions and active transitions of one or more of a plurality of power-wells of a processor; and
determination logic to determine performance loss or energy gain based at least in part on the detected information and power-on latency from one or more of the plurality of power-wells of the processor, wherein the measurement logic is to detect information about the idle transitions and the active transitions of each of the plurality of power-wells of the processor, wherein power management logic is to cause each of the plurality of power-wells to pre-wake in response to a global power-on request.