US 10,191,876 B2
Device and method for addressing, and converter
Wolfgang Kropp, Hochheim (DE); and Andreas Schiff, Tettnang (DE)
Assigned to SEW-EURODRIVE GMBH & CO. KG, Bruchsal (DE)
Filed by SEW-EURODRIVE GMBH & CO. KG, Bruchsal (DE)
Filed on Nov. 13, 2017, as Appl. No. 15/811,208.
Application 15/811,208 is a continuation of application No. 14/601,955, filed on Jan. 21, 2015, granted, now 9,817,781.
Application 14/601,955 is a continuation of application No. 12/303,106, granted, now 8,972,641, issued on Mar. 3, 2015, previously published as PCT/EP2007/004341, filed on May 16, 2007.
Claims priority of application No. 10 2006 026 972 (DE), filed on Jun. 1, 2006.
Prior Publication US 2018/0165236 A1, Jun. 14, 2018
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/38 (2006.01); G06F 12/00 (2006.01); G05B 19/042 (2006.01); H04L 12/40 (2006.01); H04L 29/12 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/385 (2013.01) [G05B 19/0423 (2013.01); G06F 12/00 (2013.01); G06F 13/4068 (2013.01); H04L 12/40006 (2013.01); H04L 29/12254 (2013.01); H04L 29/12849 (2013.01); H04L 61/2038 (2013.01); H04L 61/6027 (2013.01); G05B 2219/21027 (2013.01); G05B 2219/21043 (2013.01); G05B 2219/25428 (2013.01); G05B 2219/31121 (2013.01); H04L 2012/40215 (2013.01); H04L 2012/40221 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A system, comprising:
a device adapted to connect to a bus;
wherein the device is adapted to implement a single logical slave as a bus participant in a first mode and at least two logical slaves as bus participants in a second mode;
wherein the first mode is a standard addressing mode, and the second mode is an expanded address mode;
wherein the device includes a reversing logic adapted to shift the device from the first mode to the second mode to switch the device from a standard address to an expanded address to implement the at least two logical slaves in a single addressing process, the at least two logical slaves being made available as bus participants immediately after the addressing;
wherein the at least two logical slaves are operable in the second mode in the expanded address mode in respective cycles by an address assigned by a standard addressing signal; and
wherein the at least two logical slaves have profiles that differ from each other.