US 11,871,583 B2
Ferroelectric memory devices
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing, Inc., San Francisco, CA (US)
Filed on Sep. 17, 2021, as Appl. No. 17/478,849.
Application 17/478,849 is a continuation of application No. 17/465,792, filed on Sep. 2, 2021.
Prior Publication US 2023/0076825 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); H10B 53/10 (2023.01); H01L 49/02 (2006.01); H03K 19/185 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H10B 53/30 (2023.02) [H01L 21/76802 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 28/55 (2013.01); H01L 28/60 (2013.01); H01L 28/65 (2013.01); H03K 19/185 (2013.01); H10B 53/10 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A device comprising:
a first region comprising:
a first conductive interconnect within a first level; and
a second level above the first level, the second level comprising:
a ferroelectric memory device comprising a first height and further comprising a cylindrical shape, the ferroelectric memory device above the first conductive interconnect;
an encapsulation layer on a sidewall of the ferroelectric memory device; and
a via electrode on the ferroelectric memory device, wherein the via electrode comprises a second height;
a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
a second conductive interconnect within the first level;
an etch stop layer comprising a dielectric material in the second level;
a metal line above the etch stop layer, wherein the metal line is within the second level and wherein the metal line comprises a third height; and
a via structure coupling the metal line with the second conductive interconnect, wherein the via structure is in the second level and comprises a fourth height, wherein a combined sum of the first height and the second height is equal to a combined sum of the third height and the fourth height; and
a portion of one or more layers of the ferroelectric memory device adjacent to a sidewall of the etch stop layer at a boundary between the first region and the second region.