CPC H10B 43/35 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02)] | 20 Claims |
1. An electronic device, comprising:
memory pillars in a lower deck and in an upper deck of an array region of the electronic device comprising multiple decks, the memory pillars operably coupled to a source adjacent to the lower deck and the upper deck; and
dummy pillars in an upper deck of one or more non-array regions of the electronic device, the dummy pillars electrically isolated from the source.
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