US 11,871,575 B2
Electronic devices including pillars in array regions and non-array regions
S M Istiaque Hossain, Boise, ID (US); Christopher J. Larsen, Boise, ID (US); Anilkumar Chandolu, Boise, ID (US); Wesley O. McKinsey, Nampa, ID (US); Tom J. John, Boise, ID (US); Arun Kumar Dhayalan, Boise, ID (US); and Prakash Rau Mokhna Rau, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 14, 2022, as Appl. No. 17/806,829.
Application 17/806,829 is a continuation of application No. 16/851,638, filed on Apr. 17, 2020, granted, now 11,387,245.
Prior Publication US 2022/0310632 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/35 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
memory pillars in a lower deck and in an upper deck of an array region of the electronic device comprising multiple decks, the memory pillars operably coupled to a source adjacent to the lower deck and the upper deck; and
dummy pillars in an upper deck of one or more non-array regions of the electronic device, the dummy pillars electrically isolated from the source.