US 11,871,572 B2
Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
Shyam Surthi, Boise, ID (US); Davide Resnati, Vimercate (IT); Paolo Tessariol, Arcore (IT); Richard J. Hill, Boise, ID (US); and John D. Hopkins, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,564.
Application 17/561,564 is a division of application No. 16/548,320, filed on Aug. 22, 2019, granted, now 11,244,954.
Prior Publication US 2022/0123018 A1, Apr. 21, 2022
Int. Cl. H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 43/27 (2023.01); H01L 29/49 (2006.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/4991 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/7883 (2013.01); H01L 29/792 (2013.01); H10B 41/27 (2023.02)] 23 Claims
OG exemplary drawing
 
1. A method of forming an integrated structure, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack, the opening having a peripheral sidewall;
forming charge-blocking material adjacent the peripheral sidewall;
forming charge-storage material adjacent the charge-blocking material;
forming gate-dielectric material adjacent the charge-storage material;
forming channel material adjacent the gate-dielectric material;
removing the second material to leave first voids;
forming conductive levels within the first voids; the conductive levels having front ends with front surfaces; the front surfaces facing the charge blocking material;
after the forming of the charge-blocking material, forming high-k dielectric material to be between said front surfaces and the charge-blocking material; the high-k dielectric material being configured as first segments which are vertically-spaced from one another, with said first segments being along the front surfaces of the conductive levels and not wrapping around the front ends of the conductive levels;
removing the first material to leave second voids; and
extending the second voids through the charge-storage material to divide the charge-storage material into vertically-spaced segments.