US 11,871,561 B2
Semiconductor structure and manufacturing method of semiconductor structure
Chun-Sheng Juan Lu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 2, 2021, as Appl. No. 17/446,829.
Application 17/446,829 is a continuation of application No. PCT/CN2021/101618, filed on Jun. 22, 2021.
Claims priority of application No. 202010878114.1 (CN), filed on Aug. 27, 2020.
Prior Publication US 2022/0068936 A1, Mar. 3, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/31 (2023.02); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
word lines, located in the substrate, wherein a bit line contact hole is provided between each two adjacent word lines;
bit line contact plugs, located in the bit line contact holes; and
first isolation layers, located on side walls of the bit line contact holes and covering side walls of the bit line contact plugs,
wherein a bit line contact plug among the bit line contact plugs is a three-layer structure comprising a metal material and two layers of polycrystalline silicon, and
wherein the metal material is sandwiched between the two layers of polycrystalline silicon.