US 11,871,553 B2
Semiconductor device and stack of semiconductor chips
Shaofeng Ding, Suwon-si (KR); Jeong Hoon Ahn, Seongnam-si (KR); and Yun Ki Choi, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 14, 2021, as Appl. No. 17/474,436.
Claims priority of application No. 10-2021-0023931 (KR), filed on Feb. 23, 2021.
Prior Publication US 2022/0271045 A1, Aug. 25, 2022
Int. Cl. H01L 27/11 (2006.01); H01L 27/108 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01)
CPC H10B 10/18 (2023.02) [H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/0847 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a logic cell region and a connection region;
a dummy transistor on the connection region;
an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor;
a first metal layer on the intermediate connection layer;
an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern; and
a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region,
wherein an upper portion of the penetration contact protrudes above the etch stop layer,
the first metal layer including a first interconnection line, a second interconnection line, and a via below the second interconnection line,
the via penetrates the etch stop layer and connects the second interconnection line to the connection pattern, and
a top surface of the penetration contact is in direct contact with a bottom surface of the first interconnection line.