US 11,871,526 B2
Circuit board and method of manufacturing circuit board
Jun Dai, Qinhuangdao (CN)
Assigned to HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Qinhuangdao (CN); and Avary Holding (Shenzhen) Co., Limited., Shenzhen (CN)
Filed by HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Qinhuangdao (CN); and Avary Holding (Shenzhen) Co., Limited., Shenzhen (CN)
Filed on Feb. 16, 2022, as Appl. No. 17/672,980.
Application 17/672,980 is a division of application No. 17/022,385, filed on Sep. 16, 2020, granted, now 11,291,126.
Claims priority of application No. 202010719860.6 (CN), filed on Jul. 23, 2020.
Prior Publication US 2022/0174822 A1, Jun. 2, 2022
Int. Cl. H05K 1/02 (2006.01); H01L 23/06 (2006.01); H01F 27/22 (2006.01); H01F 27/29 (2006.01); H01F 27/32 (2006.01); H01F 27/255 (2006.01); H05K 3/46 (2006.01); H05K 1/03 (2006.01); H05K 3/00 (2006.01); H05K 3/18 (2006.01)
CPC H05K 3/467 (2013.01) [H05K 1/0298 (2013.01); H05K 1/0313 (2013.01); H05K 3/0023 (2013.01); H05K 3/188 (2013.01); H05K 2203/06 (2013.01); H05K 2203/0723 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A circuit board comprising:
a substrate comprising a base layer, a first metal layer formed on the base layer, and a seed layer formed on the base layer;
a first circuit layer located on the substrate and comprising the first metal layer and a signal layer formed on a surface of the first metal layer;
a second circuit layer coupled to the first circuit layer and comprising the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer; and
a third circuit layer coupled to the second circuit layer and comprising the seed layer and a coil formed on a surface of the seed layer, wherein a sheet resistance of the first metal layer is larger than a sheet resistance of the seed layer.