US 11,871,525 B2
Wiring board and manufacturing method for same
Yoshihiro Hasegawa, Yasu (JP)
Assigned to KYOCERA CORPORATION, Kyoto (JP)
Appl. No. 17/439,494
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Dec. 17, 2019, PCT No. PCT/JP2019/049298
§ 371(c)(1), (2) Date Sep. 15, 2021,
PCT Pub. No. WO2020/188923, PCT Pub. Date Sep. 24, 2020.
Claims priority of application No. 2019-048623 (JP), filed on Mar. 15, 2019.
Prior Publication US 2022/0159844 A1, May 19, 2022
Int. Cl. H05K 1/03 (2006.01); H05K 3/46 (2006.01); H05K 1/11 (2006.01)
CPC H05K 3/4661 (2013.01) [H05K 1/0373 (2013.01); H05K 1/116 (2013.01); H05K 2201/0209 (2013.01); H05K 2201/0338 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A wiring board comprising: at least an insulating layer containing particles of silica, and a wiring conductor layer located on the insulating layer, wherein among the particles of the silica contained in the insulating layer, some particles of the silica are partially exposed on a surface of the insulating layer, the wiring conductor layer comprises a seed layer located on the insulating layer and containing a metal, and a plated conductor layer located on the seed layer, and a non-crystalline layer of the silica and a non-crystalline layer of the metal of the seed layer are present at contact portions between exposed portions of the particles of the silica and the seed layer; wherein a thickness of the non-crystalline layer of the metal is larger than a thickness of the non-crystalline layer of the silica.