US 11,870,576 B2
Control of error correction decoder operation and usage in a receiver device
Hobin Kim, San Diego, CA (US); Hari Sankar, San Diego, CA (US); Alessandro Risso, San Diego, CA (US); Harsha Acharya, Santa Clara, CA (US); Alexei Yurievitch Gorokhov, San Diego, CA (US); and Li Zhang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 29, 2022, as Appl. No. 17/657,115.
Prior Publication US 2023/0318741 A1, Oct. 5, 2023
Int. Cl. H04L 1/00 (2006.01)
CPC H04L 1/0061 (2013.01) [H04L 1/0068 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus for wireless communication, comprising:
a memory; and
at least one processor coupled to the memory and configured to:
obtain a first set of bits of a codeword, wherein the codeword includes the first set of bits and a second set of bits, wherein the second set of bits is punctured;
recover the second set of bits based on at least the first set of bits;
perform an error detection operation on the codeword using the first set of bits and the second set of bits; and
determine whether to enable an error correction decoder based on a result of the error detection operation performed on the codeword using the first set of bits and the second set of bits.