| CPC H04B 7/18513 (2013.01) | 12 Claims |
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1. Apparatus, comprising:
one or more processors; and
one or more non-transitory memories storing instructions that, when executed with the one or more processors, cause the apparatus to perform:
receiving, on a feeder link, a downlink feeder signal comprising, in time domain, feeder link downlink slots having, in frequency domain, a feeder link bandwidth with a feeder link subcarrier spacing;
mapping the feeder link downlink slots onto a respective slot-subband in a respective service link downlink slot according to a rule; and
transmitting, on plural service links, a respective downlink service signal, wherein
the downlink service signals comprise, in the time domain, respective one or more of the service link downlink slots;
the service link downlink slots comprise, in the frequency domain, m of the slot-subbands with m being a positive integer;
in the service link downlink slots, the m slot-subbands are arranged, in the frequency domain, with a same bandwidth and with a service link subcarrier spacing; and
in the service link downlink slots, in the frequency domain, the m slot-subbands do not overlap, are continuous, and cover an entire service link bandwidth of the respective service link downlink slot; wherein
the feeder link downlink slots have a feeder link slot duration;
the service link downlink slots have a service link slot duration longer than the feeder link slot duration;
the feeder link subcarrier spacing is larger than the service link subcarrier spacing;
the feeder link slots comprise respective symbols; and
the slot-subbands comprise the symbols of the feeder link downlink slot mapped onto the respective slot-subband.
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