CPC H04B 1/7083 (2013.01) [H04B 1/7093 (2013.01); H04J 11/0073 (2013.01); H04J 11/0076 (2013.01); H04J 13/0025 (2013.01); H04J 13/0029 (2013.01); H04L 27/2607 (2013.01); H04W 72/0466 (2013.01); H04B 2001/70935 (2013.01)] | 32 Claims |
1. A device comprising:
a processor configured to:
obtain a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence; and
determine a cell identity (ID) NID based on the PSS and the SSS, wherein the cell ID NID satisfies: NID=NID,max(2)NID(1)+NID(2), and
wherein NID(2) is associated with the PSS sequence, and NID(1) is associated with a first cyclic shift m0 and a second cyclic shift m1 of the SSS sequence; and
wherein the first cyclic shift m0 and the second cyclic shift m1 satisfy:
wherein:
g is an integer equal to or larger than 1;
L′ is 112;
NID(1)∈{0, 1, 2, . . . , NID,max(1)−1}; and
NID(2)∈{0, 1, . . . , NID,max(2)−1}.
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