US 11,870,461 B2
Failure-tolerant error correction layout for memory sub-systems
Wei Wu, San Diego, CA (US); Zhenlei Shen, Milpitas, CA (US); and Zhengang Chen, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 3, 2022, as Appl. No. 17/880,144.
Application 17/880,144 is a continuation of application No. 16/205,075, filed on Nov. 29, 2018, granted, now 11,438,012.
Prior Publication US 2022/0376709 A1, Nov. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/15 (2006.01); G06F 11/10 (2006.01)
CPC H03M 13/1525 (2013.01) [G06F 11/1076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a plurality of codewords of an error correcting code for a memory sub-system;
dividing each of the plurality of codewords of the error correcting code into a plurality of segments, wherein the plurality of segments are distributed across a plurality of dies of the memory sub-system;
calculating an exclusive-OR (XOR) value based on a combination of the plurality of codewords;
applying respective shifts to the plurality of segments of each of the plurality of codewords to arrange the plurality of segments into a first layout spread across the plurality of dies in the memory sub-system, wherein a number of codewords in the plurality of codewords is equal to a number of dies in the plurality of dies, and wherein a codeword segment along a column or row of the first layout is unique; and
forming an error correcting (EC) layout across the plurality of dies, wherein the first layout constitutes at least a portion of the EC layout, wherein the EC layout stores the plurality of segments of the plurality of codewords and the calculated XOR value.