US 11,870,449 B2
Systems and methods for calibrating digital phase-locked loops
Elan Banin, Raanana M (IL); Yaniv Cohen, Hod Hasharon (IL); Ofir Degani, Nes-Ammin (IL); and Igal Kushnir, Hod-Hasharon (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/638,739
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 28, 2019, PCT No. PCT/US2019/068847
§ 371(c)(1), (2) Date Feb. 25, 2022,
PCT Pub. No. WO2021/133415, PCT Pub. Date Jul. 1, 2021.
Prior Publication US 2022/0393690 A1, Dec. 8, 2022
Int. Cl. H03L 7/099 (2006.01); G06F 1/08 (2006.01); H03L 7/093 (2006.01)
CPC H03L 7/0992 (2013.01) [G06F 1/08 (2013.01); H03L 7/093 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A clock generator calibration system, comprising:
a phased-locked loop (PLL) configured to generate an output clock signal; and
a correction circuit, comprising:
a code ramp configured to generate digital-to-time converter (DTC) codes; and
a statistics processor configured to:
sample values of a digital signal of the PLL;
determine a distribution of the sampled values of the digital signal of the PLL per each respectively received one of the DTC codes; and
generate a correction signal based on the distribution,
wherein the correction circuit is configured to generate a control signal based on the correction signal and a generated DTC code from among the generated DTC codes, and to cause the PLL to adjust a frequency signal of the PLL to provide an adjusted frequency signal based on the digital signal of the PLL, the digital signal being generated based on the adjusted frequency signal.