CPC H03K 19/0956 (2013.01) [H01L 25/065 (2013.01); H01L 27/0207 (2013.01); H01L 27/105 (2013.01); H01L 27/11807 (2013.01); H01L 28/00 (2013.01); H01L 31/032 (2013.01); H01L 31/0376 (2013.01); H01L 31/072 (2013.01); H01L 31/074 (2013.01); H03K 19/01707 (2013.01); H03K 19/0948 (2013.01); H03K 19/17728 (2013.01); H10B 12/50 (2023.02); H10B 20/00 (2023.02); H10B 20/38 (2023.02); H10B 20/60 (2023.02); H10B 20/65 (2023.02); H10B 41/40 (2023.02); H10B 41/49 (2023.02); H01L 28/20 (2013.01); H01L 2924/0002 (2013.01); Y02E 10/50 (2013.01)] | 17 Claims |
1. An integrated circuit implementing a Schottky-CMOS multiplexer (MUX) gate system, the integrated circuit comprising:
a plurality of inputs coupled with a first stage of the integrated circuit, the first stage including a plurality of first Schottky diodes and a plurality of N-type transistors, wherein each input is coupled with a respective first Schottky diode and a respective N-type transistor;
a plurality of outputs of the first stage of the integrated circuit coupled with a second stage of the integrated circuit, the second stage including a plurality of second Schottky diodes and a plurality of P-type transistors, wherein each output is coupled with a respective second Schottky diode and a respective P-type transistor;
a plurality of outputs of the second stage of the integrated circuit coupled with a set of transistors including a P-type transistor and an N-type transistor; and
an output of the set of transistors coupled with an output of the MUX gate system.
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