US 11,870,438 B2
Schottky-CMOS asynchronous logic cells
Augustine Wei-Chun Chang, Mountain View, CA (US); and Pierre Dermy, Reno, NV (US)
Assigned to SCHOTTKY LSI, INC., Mountain View, CA (US)
Filed by Schottky LSI, Inc., Mountain View, CA (US)
Filed on May 24, 2022, as Appl. No. 17/752,673.
Application 13/931,315 is a division of application No. 12/343,465, filed on Dec. 23, 2008, granted, now 8,476,689, issued on Jul. 2, 2013.
Application 17/752,673 is a continuation of application No. 16/883,753, filed on May 26, 2020, granted, now 11,342,916.
Application 16/883,753 is a continuation of application No. 15/817,026, filed on Nov. 17, 2017, granted, now 10,666,260, issued on May 26, 2020.
Application 15/817,026 is a continuation of application No. 15/484,040, filed on Apr. 10, 2017, granted, now 9,853,643, issued on Dec. 26, 2017.
Application 15/484,040 is a continuation in part of application No. 15/358,049, filed on Nov. 21, 2016, granted, now 9,806,072, issued on Oct. 31, 2017.
Application 15/358,049 is a continuation in part of application No. PCT/US2015/055020, filed on Oct. 9, 2015.
Application 15/358,049 is a continuation of application No. 14/793,690, filed on Jul. 7, 2015, granted, now 9,502,379, issued on Nov. 22, 2016.
Application 14/793,690 is a continuation of application No. 13/931,315, filed on Jun. 28, 2013, granted, now 9,077,340, issued on Jul. 7, 2015.
Claims priority of provisional application 62/062,800, filed on Oct. 10, 2014.
Prior Publication US 2022/0286134 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/09 (2006.01); H03K 19/0956 (2006.01); H01L 25/065 (2023.01); H01L 27/02 (2006.01); H01L 27/105 (2023.01); H01L 27/118 (2006.01); H01L 49/02 (2006.01); H01L 31/032 (2006.01); H01L 31/0376 (2006.01); H01L 31/072 (2012.01); H01L 31/074 (2012.01); H03K 19/017 (2006.01); H03K 19/0948 (2006.01); H03K 19/17728 (2020.01); H10B 12/00 (2023.01); H10B 20/00 (2023.01); H10B 41/40 (2023.01); H10B 41/49 (2023.01)
CPC H03K 19/0956 (2013.01) [H01L 25/065 (2013.01); H01L 27/0207 (2013.01); H01L 27/105 (2013.01); H01L 27/11807 (2013.01); H01L 28/00 (2013.01); H01L 31/032 (2013.01); H01L 31/0376 (2013.01); H01L 31/072 (2013.01); H01L 31/074 (2013.01); H03K 19/01707 (2013.01); H03K 19/0948 (2013.01); H03K 19/17728 (2013.01); H10B 12/50 (2023.02); H10B 20/00 (2023.02); H10B 20/38 (2023.02); H10B 20/60 (2023.02); H10B 20/65 (2023.02); H10B 41/40 (2023.02); H10B 41/49 (2023.02); H01L 28/20 (2013.01); H01L 2924/0002 (2013.01); Y02E 10/50 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit implementing a Schottky-CMOS multiplexer (MUX) gate system, the integrated circuit comprising:
a plurality of inputs coupled with a first stage of the integrated circuit, the first stage including a plurality of first Schottky diodes and a plurality of N-type transistors, wherein each input is coupled with a respective first Schottky diode and a respective N-type transistor;
a plurality of outputs of the first stage of the integrated circuit coupled with a second stage of the integrated circuit, the second stage including a plurality of second Schottky diodes and a plurality of P-type transistors, wherein each output is coupled with a respective second Schottky diode and a respective P-type transistor;
a plurality of outputs of the second stage of the integrated circuit coupled with a set of transistors including a P-type transistor and an N-type transistor; and
an output of the set of transistors coupled with an output of the MUX gate system.