US 11,870,247 B2
Failsafe input/output electrostatic discharge protection with diodes
Tzu-Heng Chang, New Taipei (TW); and Hsin-Yu Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 24, 2021, as Appl. No. 17/484,086.
Claims priority of provisional application 63/160,049, filed on Mar. 12, 2021.
Prior Publication US 2022/0294211 A1, Sep. 15, 2022
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01)
CPC H02H 9/046 (2013.01) [H01L 27/0248 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of providing electrostatic discharge (ESD) protection, comprising:
receiving an input current from an input/output (I/O) pin of a plurality of I/O pins;
responding to an ESD event when a voltage threshold at the I/O pin is met and clamping a voltage to a holding voltage;
during the ESD event, the ESD protection operating in either pull to VDD (PD) mode or pull to VSS (PS) mode;
wherein the PS mode is configured to clamp the voltage at the holding voltage by an ESD path from the I/O pin to VSS through a first series of diodes,
wherein the PD mode is configured to clamp the voltage at a second holding voltage through an ESD path from the I/O pin to VDD through a second series of diodes, and
wherein the first series of diodes include a plurality of shared diodes shared among the plurality of I/O pins.