US 11,870,163 B2
Antenna package using ball attach array to connect antenna and base substrates
Jimin Yao, Chandler, AZ (US); Robert L. Sankman, Phoenix, AZ (US); Shawna M. Liff, Scottsdale, AZ (US); Sri Chaitra Jyotsna Chavali, Chandler, AZ (US); William J. Lambert, Chandler, AZ (US); and Zhichao Zhang, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 25, 2022, as Appl. No. 17/705,182.
Application 17/705,182 is a continuation of application No. 16/635,148, granted, now 11,355,849, previously published as PCT/US2017/054395, filed on Sep. 29, 2017.
Prior Publication US 2022/0216611 A1, Jul. 7, 2022
Int. Cl. H01Q 9/04 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01)
CPC H01Q 9/0414 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/66 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6677 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An electronic assembly, comprising:
a first region, including:
a first antenna patch,
a second antenna patch, and
multiple first metal portions coplanar with the first antenna patch;
multiple second metal portions coplanar with the second antenna patch;
multiple third metal portions, wherein individual ones of the third metal portions are between a corresponding individual one of the first metal portions and a corresponding one of the second metal portions;
a second region including a conductive structure, wherein the conductive structure includes a first conductive via; and
a third region between the first region and the second region, wherein the third region includes a second conductive via in conductive contact with the conductive structure and with the first antenna patch.